1. Field of the Invention
The present invention relates to an interface circuit for a serial bus, and more particularly, to an interface circuit for a serial bus for reducing leakage current.
2. Description of the Prior Art
A bus is used for transmitting data, information, addresses, or a clock between a master device and a slave device. There are two types of bus—serial and parallel. A serial bus can transmit a plurality of data simultaneously, and thus save more pins compared to the parallel bus. In the serial bus system, the master device (slave device) utilizes the interface circuit to output a single end logic signal, and the slave device (master device) determines a bit state of a received signal according to a logic level of the received signal.
Please refer to FIG. 1, which is a schematic diagram of an interface circuit 10 for an Inter-Integrated Circuit (I2C) bus. The interface circuit 10 driven by a voltage V2 includes a current source 100, an N type metal oxide semiconductor (NMOS) N1 with a threshold voltage Vtn and a Schmitt trigger 120. A master device 12 driven by a voltage V1 is used for transmitting a data signal SDA (or a clock signal) to the interface circuit 10, where the data signal SDA has a maximum voltage level of V1. The NMOS N1, as a switching circuit, receives the data signal SDA from the gate electrode and outputs a voltage signal Vx from the drain electrode. As the NMOS N1 conducts, the current source 100 provides a current IV2 with intensity of I. The Schmitt trigger 120, driven by the voltage V2 as well, is used to converting the voltage signal Vx into the data signal SDA_IN, which is a square wave signal having the maximum voltage level of V2.
Please refer to FIG. 2, which is a schematic diagram of signal timing of the interface circuit 10 shown in FIG. 1. The related signals from top to bottom are illustrated as follows: data signal SDA, voltage signal Vx, data output signal SDA_IN and current IV2. As shown in FIG. 2, the current IV2 passes through the NMOS N1 to the grounded terminal when the data signal SDA conducts the NMOS N1. At this moment, the voltage signal Vx is equal to a grounding voltage across the grounded terminal, and the current IV2 is equal to I. When the data signal SDA has the NMOS N1 shut, the current IV2 is equal to 0, and the voltage signal Vx is equal to V2.
Thus, when the data signal SDA operates at the maximum voltage level V1, the current IV2 operates at the maximum current level of I as well. This causes power consumption in the interface circuit 10. Furthermore, the master device 12 holds the data signal SDA at voltage level V1 during standby. In this situation, the current IV2 acts as a leakage current. Also, the Schmitt trigger 120 encounters the same leakage current situation.